The latest version of CodeSonar, Version 5.3

The latest version of CodeSonar, Version 5.3

Improves on Functional Safety, MISRA Support, C++ Parsing and Visualization

The latest version of GrammaTech CodeSonar, Version 5.3, continues our commitment to being the go-to provider for static application security testing (SAST) and the static analysis tool of choice for improving software safety, security and quality.

This release of CodeSonar includes improvements in support for Android, NetBSD 8, Visual Studio 19, the CWE 4.0 mapping and many usability improvements.

TRACE32 supports SDMA in i.MX Application Processors

TRACE32 supports SDMA in i.MX Application Processors

Lauterbach are pleased to announce support for the SDMA engine in the NXP iMX family of processors. The IMX devices are designed for demanding applications in various fields, including Automotive, Avionics and Transport, Robotics, Building Control, Healthcare, and General HMI solutions.

This feature will be available from the 2nd May 2020 to Lauterbach customers. Initially, support for iMX6 is included but this will be extended to support other iMX devices.

Free Micro CANopen Libraries for NXP Microcontrollers

Free Micro CANopen Libraries for NXP Microcontrollers

Embedded Systems Academy (EmSA) and NXP® Semiconductors announce the integration of the free-to-use EmSA Micro CANopen libraries into the NXP MCUXpresso Software Development Kit (SDK) for developing with NXP’s microcontrollers (MCU) and crossovers based on Arm® Cortex®-M.

For more information about the NXP microcontrollers currently supported by EmSA’s free to use CANopen libraries and video tutorials, visit www.em-sa.com/nxp

OS and RTE Profiling for TriCore™ AURIX™

OS and RTE Profiling for TriCore™ AURIX™

Vector and Lauterbach have jointly developed a solution for Vector’s AUTOSAR classic basic software MICROSAR. The main idea is to configure trace hooks in such a way that trace data with timestamps are generated for all task switches, all task state changes, all ISR events, and all Runnable starts/ends.

 

TRACE32 and Python – Improved Python support

TRACE32 and Python

With the improved Python support we want to enhance two main areas:

• The Remote API in Python enables test frame developers to run complex tests via a
TRACE32 backend using a native Python script (see picture to the left).
• The new ability to edit and run Python scripts in TRACE32 gives developers direct
access to features from the Python scripting environment (see picture to the right).

SEGGER releases Floating-Point Library for RISC-V

SEGGER releases Floating-Point Library for RISC-V

SEGGER’s stand-alone Floating-Point Library is now extended by an assembly-optimized variant for RISC-V.

The floating-point library contains the complete set of arithmetic functions, hand coded and fully optimized in assembly language for RISC-V. The complete set of high-level mathematical functions is written in C, and uses advanced algorithms to maximize performance.

All functionality is fully verified, for both single and double precision operations.

The RISC-V variant, like the variant for ARM, is optimized for both high speed and small code size. The balance between size and speed can be configured at library build time. The SEGGER Floating-Point Library for RISC-V is much smaller than equivalent open-source libraries while achieving up to 100 times the performance on some operations.

Addition of support for NXP S32G

Addition of support for NXP S32G

Lauterbach, the world’s leading debug tools provider, is pleased to announce the addition of support for the NXP S32G Vehicle Network Processor family to their TRACE32 debug and trace tools. The S32G family provides hardware security, ASIL D safety and high-performance processing for a range of automotiveapplications.

Workshop: Develop Secure Cortex-M Application

Workshop: Develop Secure Cortex-M Application

Gain practical hands-on experience on accelerating the performance and security of your application on modern Cortex-M MCU´s.

 

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This hands-on workshop will showcase the key features of the NXP’s Most Performance Efficient Cortex-M33-based MCU with Advanced Security and Integration.

The LPC5500 MCU Series leverages the most recent Arm Cortex-M33 technology. It combines significant product architecture enhancements and greater integration over previous generations; offering dramatic power consumption improvements and advanced security features. It includes SRAM PUF based root of trust and provisioning, real time

execution from encrypted images (internal flash), and asset protection with Arm TrustZone-M.

OP-TEE awareness from Arm® Cortex-A® cores

OP-TEE awareness from Arm® Cortex-A® cores

Lauterbach, the leading manufacturer of microprocessor development tools, has announced that they have extended the kernel awareness for OP-TEE, the open source Trusted Execution Environment (TEE) running on Arm® Cortex-A® cores. OP-TEE was originally developed by ST Ericsson and is, today, primarily owned and maintained by Linaro.

Using the new OP-TEE awareness for TRACE32, the developer can visualize the lists of Trusted Applications with detailed information such as the Universally Unique Identifier UUID, the load address and segments. The included symbol autoloader handles the automatic loading and relocation of debug symbols that correspond to running Trusted Applications.

By loading the OP-TEE awareness in conjunction with the Linux awareness, seamless debugging of the total system can be achieved. TRACE32 is able to map the awareness and the debug symbols of each OS to the respective zone: secure or non-secure. It is possible to visualize each Linux task or Trusted Application at any time, even if it is currently not active.

All features of the TRACE32 awareness for OP-TEE are available without requiring any additional target configuration or any hooks or patches within the OP-TEE OS itself. The philosophy of TRACE32 is for the application to behave exactly the same in the debug environment as on the final product; only this way can 100% certainty of testing be achieved.

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